DDR4 Notes, part 1

Jan 30, 2023

NXP docs are meh, this TI document was very helpful.
A scary number of pins are NC and that’s okay. You can ignore a lot of features, especially if your chip doesn’t support it…. probably, I mean I haven’t really tested this yet but I’m making an assuption and betting my wallet on it.
Micron’s datasheet for their SDP packages (at least I think they’re SDP, because the other datasheets say TwinDie) contain decent information.
Micron needs to redo their product naming because they have the exact same part number header for completely different datasheets
Everyone thinks fly-by routing is cool, don’t do T routing
Bit and byte swapping exists but there’s some restrictions on it’s use
LPDDR4 x16 packages seem to be all out of stock
Non-LP DDR4 has reasonably high capacities in x8, best I could get to was 4gigs of RAM for a 16 bit bus
What the fuck does A17 do?
Why doesn’t the 11x11mm i.MX8M Nano UltraLite support DDR4 parity? Do I care?
Apparently people disable CRC to allow bit swapping, that sounds kind of drastic, is that even okay?
Yeah I definitely bit off more than I can chew.

Oh, and uhm

Cadence Allegro casually decides to set a global environment variable called “HOME” and assumes this won’t break a million things (in my case, git and a bunch of cygwin/mingw/whatever this shit is). Delete it. Either the variable or allegro, your call.

Updates, Jan 31st, 2023

The TwinDie packages that micron makes aren’t “traditional” DDP packages and do not use the second CKE, CS_n or ODT pins.
Use the 96 pin packages. Somehow makes things easier to breathe.
Some chips work better with 78 pin, some with 96. If one’s not working, try the other, topology will shine down upon you.